Design Verification Engineer
MaxLinear
Paterna, ES
hace 4 días

Responsibilities

MaxLinear is seeking a Verification Engineer to join the ASIC team in Valencia design center. In this role, will work on the verification for digital SoC and signal processing chipsets with integrated analog components and high-speed networking interfaces.

  • Experience in verification strategy development and execution for large SoCs and signoff with coverage metrics
  • Knowledge of UVM methodology, SystemC and System Verilog
  • Implementation of randomized and directed random testbenches for networking and multi-cpu environments
  • Experience with gate level simulations of delay annotated netlists
  • Knowledge of verification IP and functional coverage techniques
  • Experience with signoff of SoC designs with coverage metrics
  • Experience with design would be a plus
  • Qualifications

  • Strong logical and creative problem-solving skills with excellent analytical and debugging skills
  • Must be a flexible self-starter who can ramp up with new technologies, products, etc.
  • Motivated, and able to work effectively under pressure
  • Good written and oral communication skills
  • MS CS / EE degree or Ph.D.
  • We are open to new grads and senior engineers
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