Context And Mission
BSC is looking for 5 talented and motivated professionals with expertise in ASIC design and IP integration for a European HPC accelerator.
The design is based on RISC-V architecture. This is a project to build an FPGA-based emulator for an energy-efficient Exascale system. Key Duties
Knowledge of high-speed low-power design techniques. Logic synthesis and timing closure, is a plus. System MultiProcessors related topics such as coherency and consistency.
RTL Design (Functional / Structural, Partitioning, Simulation, Regression); Tools : Modelsim, VCS. Proficiency in Verilog / VHDL, and end-to-end design methodologies is required.
3rd Party IP integration. Experience in taking ASIC (gate array, library-based, and / or full custom) designs through to production is a plus.
Strong scripting / programming in csh / bash. Tcl, Python, and C / C++ is a plus. Agile development and open source development, deployment, and support, including GitHub or equivalent.
Fluency in English is essential, Spanish is welcome.
Ability to think creatively. Ability to work independently and make decisions. Ability to take initiative, prioritize and work under set deadlines and pressure.
Applications procedure and process
All applications must be made through BSC website and contain :
In accordance with the OTM-R principles, a gender-balanced recruitment panel is formed for every vacancy at the beginning of the process.
After reviewing the content of the applications, the panel will start the interviews, with at least one technical and one administrative interview.
A profile questionnaire as well as a technical exercise may be required during the process.
The panel will make a final decision and all candidates who had contacts with them will receive a feedback with details on the acceptance or rejection of their profile.